1. Field of the Invention
This invention relates to a method of manufacturing a semiconductor article that can suitably be used for producing a semiconductor device such as a semiconductor integrated circuit, a solar cell, a semiconductor laser device or a light emitting diode. More particularly, it relates to a method of manufacturing a semiconductor article comprising a step of transferring a semiconductor layer onto a substrate.
2. Related Background Art
Semiconductor articles are popular in terms of semiconductor wafers, semiconductor substrates and various semiconductor devices and include those adapted for producing semiconductor devices by utilizing the semiconductor region thereof and those used as preforms for producing semiconductor devices.
Some semiconductor articles of the type under consideration comprise a semiconductor layer arranged on an insulator.
The technology of forming a single crystal silicon semiconductor layer on an insulator is referred to as silicon on insulator (SOI) technology, which is widely known. Various research has been done to exploit the remarkable advantages of SOI that cannot be achieved by using the bulk Si substrates that are used for producing ordinary Si integrated circuits. The advantages of the SOI technology include:
1. the ease of dielectric isolation that allows an enhanced degree of integration; PA1 2. the excellent resistivity against radiation; PA1 3. a reduced floating capacitance that allows a high device operation speed; PA1 4. the omission of the well forming step; PA1 5. the effect of latch up prevention; and PA1 6. the possibility of producing fully depleted field effect transistors using the thin film technology. The advantages of the SOI technology are thoroughly discussed in the Special Issue: "Single-crystal silicon on non-single-crystal insulators"; edited by G. W. Cullen, Journal of Crystal Growth, volume 63, No. 3, pp. 429-590 (1983). PA1 (1) polishing; PA1 (2) local plasma etching; and PA1 (3) selective etching. PA1 applying sufficiently strong tensile force or pressure onto a surface of the combined wafers along a direction perpendicular to the surface; PA1 applying wave energy in the form of an ultrasonic wave or the like to the combined wafers; PA1 causing the porous layer to be exposed at an end surface of the combined wafers, etching the porous Si layer to a certain extent and inserting the edge of a blade; PA1 causing the porous layer to be fully exposed at an end surface of the wafers, soaking the porous Si layer with liquid that may be water and causing the liquid to expand by entirely heating or cooling the combined wafers; and PA1 applying force to the first (or second) substrate along a direction parallel to the second (or first) substrate in order to destroy the porous Si layer.
In recent years, a number of reports have been published on the SOI technology for providing substrates that can realize high speed operation and low power consumption for MOSFETs (IEEE SOI conference 1994). The process of manufacturing a semiconductor device can be significantly shortened by using the SOI structure if compared with the corresponding process of manufacturing a device on a bulk Si wafer, because of the implementation of a very simplified device isolation step. Thus, the use of the SOI technology can provide a significant cost reduction in manufacturing a semiconductor device, particularly in terms of the wafer cost and the process cost if viewed from the conventional technology of manufacturing a MOSFET or an IC on a bulk Si substrate, to say nothing of the remarkable performance of such a semiconductor device.
Fully depleted MOSFETs are very promising for achieving high speed operation and low power consumption if provided with improved drive power. Generally speaking, the threshold voltage (Vth) of a MOSFET is determined as a function of the impurity concentration of its channel section but, in the case of a fully depleted (FD) MOSFET, the characteristics of the depletion layer are influenced by the SOI film thickness. Therefore, the SOI film thickness has to be rigorously controlled in order to improve the yield of manufacturing LSIs.
Meanwhile, a device formed on a compound semiconductor shows a remarkable level of performance that cannot be expected from silicon, particularly in terms of high speed operation and light emission. Such devices are currently formed by means of epitaxial growth on a compound semiconductor substrate that may be made of GaAs or a similar compound. However, a compound semiconductor substrate is costly and mechanically not very strong, so that it is not adapted to produce a large wafer.
Thus, efforts have been made to form a compound substrate by hetero-epitaxial growth on a Si wafer that is inexpensive, mechanically strong and good for producing a large wafer.
Research on forming SOI substrates became significant in the 1970s. Initially, attention was paid to the technique of producing single crystal silicon by epitaxial growth on a sapphire substrate (SOS: silicon on sapphire), that of producing an SOI structure through full isolation by porous oxidized silicon (FIPOS) and the oxygen ion implantation technique. The FIPOS method comprises steps of forming an islanded N-type Si layer on a P-type single crystal Si substrate by proton/ion implantation (Imai et al., J. Crystal Growth, Vol. 63,547 (1983)) or by epitaxial growth and patterning, transforming only the P-type Si substrate into a porous substrate by anodization in a HF solution, shielding the Si islands from the surface, and then subjecting the N-type Si islands to dielectric isolation by accelerated oxidation. This technique is, however, accompanied by a problem that the isolated Si region is defined before the process of producing devices, therefore restricting the freedom of device design.
The oxygen ion implantation method is also referred to as the SIMOX method, which was proposed by K. Izumi for the first time. With this technique, oxygen ions are implanted into a Si wafer to a concentration level of 10.sup.17 to 10.sup.18 /cm.sup.2 and then the latter is annealed at high temperature of about 1,320.degree. C. in an argon/oxygen atmosphere. As a result, the implanted oxygen ions are chemically combined with Si atoms to produce a silicon oxide layer that is centered at a depth corresponding to the projection range (Rp) of the implanted ions. Under this condition, an upper portion of the Si oxide layer that is turned into an amorphous state by the oxygen ion implantation is recrystallized to produce a single crystal Si layer. While the surface Si layer used to show a defect rate as high as 10.sup.5 /cm.sup.2, a recent technological development has made it possible to reduce the defect rate down to about 10.sup.2 /cm.sup.2 by selecting a rate of oxygen implantation of about 4.times.10.sup.17 /cm.sup.2. However, the allowable range of energy infusion and that of ion implantation are limited if the film quality of the Si oxide layer and the crystallinity of the surface Si layer are to be held to respective desired levels and hence the film thickness of the surface Si layer and that of the buried Si oxide (BOX; buried oxide) layer are allowed to take only limited values. In other words, a process of sacrifice oxidation or epitaxial growth is indispensable to realize a surface Si layer having a desired film thickness. Such a process, in turn, gives rise to a problem of uneven film thickness due to the intrinsic adverse effect of the process.
There have been reports saying that SIMOX can produce defective Si oxide regions in the Si oxide layer that are referred to as pipes. One of the possible causes of the phenomenon may be foreign objects such as dust introduced into the layer at the time of ion implantation. The device produced in a pipe region can show degraded characteristics due to the leak current between the active layer and the underlying substrate.
The SIMOX technique involves the use of a large volume of ions that is by far greater than the volume used in the ordinary semiconductor process and hence the ion implantation process may take a long time if a specifically designed apparatus is used for it. Since the ion implantation process is performed typically by means of raster scan of an ion beam showing a predetermined flow rate of electric current or by spreading an ion beam, a long time may be required for processing a large wafer. Additionally, when a large wafer is processed at high temperature, the slip problem due to an uneven temperature distribution within the wafer can become very serious. Since the SIMOX process requires the use of extraordinary high temperature that is as high as 1,320.degree. C., which is not observed in the ordinary Si semiconductor process, the problem of uneven temperature distribution will become more serious if a large wafer has to be prepared unless a highly effective apparatus is not realized.
Beside the above-described known techniques of forming SOI, a technique of bonding a single crystal Si substrate to another single crystal Si substrate that has been thermally oxized to produce an SOI structure has been proposed recently. This method requires the use of an active layer having an even thickness for the devices to be formed on it. More specifically, a single crystal Si substrate that is as thick as several hundred micrometers has to be made as thin as several micrometers or less. Three techniques have been known for thinning a single crystal Si layer that include:
It is difficult to achieve an even film thickness by means of the polishing technique. Particularly, the mean deviation in the film thickness can be as large as tens of several percent to make the technique unfeasible when the film is thinned to an order of sub-micrometer. This problem will become more significant for wafers having a large diameter.
The technique of local plasma etching is typically used in combination with that of polishing. More specifically, the film is thinned by means of polishing to about 1 to 3 .mu.m and the distribution of film thickness is determined by observing the film thickness at a number of points. Then, the film is subjected to an etching operation where the film is scanned with plasma of SF.sub.6 particles having a diameter of several millimeters, correcting the distribution of film thickness, until a desired film thickness is obtained. There has been a report that the distribution of film thickness can be confined within about .+-.10 nm or less by means of this technique. However, this process is accompanied by a drawback that, if foreign objects are present on the substrate in the form of particles during the plasma etching, they operate as etching masks to produce projections on the substrate when the etching operation is over.
Additionally, since the substrate shows a coarse surface immediately after the etching operation, a touch-polishing operation has to be conducted on the surface after the end of the plasma etching and the operation is controlled only in terms of its duration. Then, again the problem of deviations in the film thickness due to polishing arises. Still additionally, a polishing agent typically containing colloidal silica is used for the polishing operation and hence the layer for making an active layer is directly scraped by the polishing agent so that a crushed and/or distorted layer may be produced. The throughput of the process can be significantly reduced when large wafers are treated because the duration of the plasma etching operation is prolonged as a function of the surface area of the wafer being processed.
Selective etching involves the use of a film configuration for the substrate to be thinned that comprises one or more film layers adapted to selective etching. For example, assume that a P.sup.+ -Si thin layer containing boron by more than 10.sup.19 /cm.sup.3 and a P-type Si thin layer are made to grow sequentially on a P-type substrate by means of epitaxial growth to produce a first substrate, which is then bonded to a second substrate with an insulation layer interposed therebetween, the insulation layer being typically an oxide film, and that the rear surface of the first substrate is made sufficiently thin in advance by scraping and polishing. Subsequently, the P.sup.+ -layer is exposed by selectively etching the overlying P-type layer and then the P-type substrate is exposed by selectively etching the P.sup.+ -layer to produce an SOI structure. This technique is discussed in detail in a report by Maszara (W. P. Maszara, J. Electrochem. Soc., Vol. 138,341 (1991)).
While the selective etching technique is effective for producing a thin film with an even film thickness, it is accompanied by the drawbacks as identified below.
The selective etching ratio is not satisfactory and will be as low as 10.sup.2 at most.
A touch-polishing operation is required to smooth the surface after the etching operation because of the coarse surface produced by the etching operation. Therefore, the film thickness can lose the uniformity as it is reduced by polishing. Particularly, while the polishing operation is controlled by the duration of the operation, it is difficult to rigorously control the operation because the polishing rate can vary significantly from time to time. Thus, this problem becomes significant when forming an extremely thin SOI layer that is as thin as 100 nm.
The produced SOI layer can show a poor crystallinity due to the use of a film forming technique that involves ion implantation and epitaxial or hetero-epitaxial growth on a Si layer that is densely doped with B. Additionally, the bonded surface of the substrate may show a degree of smoothness that is inferior relative to that of a conventional Si wafer (C. Harendt, et al., J. Elect. Mater. Vol. 20,267 (1991), H. Baumgart, et al., Extended Abstract of ECS first International Symposium of Wafer Bonding, pp-733 (1991), C. E. Hunt, Extended Abstract of ECS first International Symposium of Wafer Bonding, pp-696 (1991)). Still additionally, there is a problem that the selectivity of the selective etching technique heavily depends on the concentration difference among the impurities such as boron contained in the substrate and the steepness of the concentration profile of the impurities along the depth of the substrate. Therefore, if the bonding anneal is conducted at high temperature to improve the bonding strength of the layers and the epitaxial growth is carried out also at high temperature to enhance the crystallinity of the SOI layer, the concentration profile of the impurities along the depth becomes flattened to reduce the selectivity of the etching operation. Simply stated, the improvement of the etching selectivity and hence that of the crystallinity and the improvement of the bonding strength are conflicting requirements that cannot be met at the same time.
Under these circumstances, the inventors of the present invention proposed a novel method of manufacturing a semiconductor article in Japanese Patent Application Laid-Open No. 5-21338. According to the invention, the proposed method is characterized by forming an article by arranging a nonporous single crystal semiconductor region on a porous single crystal semiconductor region, bonding the surface of a material carrying an insulating material thereon to the corresponding surface of said porous single crystal semiconductor region and subsequently removing said porous single crystal semiconductor region by etching.
T. Yonehara et al., who are the inventors of the present invention, also reported a bonded SOI that is excellent in terms of even film thickness and crystallinity and adapted to batch processing (T. Yonehara et al., Appl. Phys. Lett. Vol. 64,2108 (1994)). Now, the proposed method of manufacturing a bonded SOI will be summarily described below by referring to FIGS. 3A through 3C of the accompanying drawings.
The proposed method uses a porous layer 32 formed on a first Si substrate 31 as a layer to be selectively etched. After forming a nonporous single crystal Si layer 33 on the porous layer 32 by epitaxial growth, it is bonded to a second substrate 34 with a Si oxide layer 35 interposed therebetween (FIG. 3A). Then, the porous Si layer is exposed over the entire surface area of the first substrate by scraping off the first substrate from the rear side (FIG. 3B). The exposed porous Si is then etched out by means of a selective etching solution typically containing KOH or HF+H.sub.2 O.sub.2 (FIG. 3C). Since the selective etching ratio of the operation of etching the porous Si layer relative to the bulk Si layer (nonporous single crystal Si layer) can be made as high as hundreds of thousands with this technique, the nonporous single crystal Si layer formed on the porous layer in advance can be transferred onto the second substrate to produce a SOI substrate without reducing the thickness of the nonporous single crystal Si layer. Thus, the uniformity of the film thickness of the SOI substrate is determined during the epitaxial growth step. According to a report by Sato et al., since a CVD system adapted to an ordinary semiconductor process can be used for the epitaxial growth, a degree of uniformity of the film thickness as high as 100 nm.+-.2% can be realized. Additionally, the epitaxial Si layer shows an excellent crystallinity of about 3.5.times.10.sup.2 /cm.sup.2.
Since the selectivity of any conventional selective etching technique heavily depends on the concentration difference among the impurities contained in the substrate and the steepness of the concentration profile of the impurities along the depth of the substrate as described above, the temperature of the heat treatment (for bonding, epitaxial growth, oxidation and so on) is limited to as low as 800.degree. C. at most because the impurity concentration profile becomes flattened above that temperature limit. On the other hand, the etching rate of the proposed etching technique is mainly determined by the structural difference between the porous layer and the bulk layer so that the heat treatment is not subjected to such a rigorous limitation and temperature as high as 1,180.degree. C. can be used. It is known that a heat treatment process conducted after the bonding operation can remarkably improve the bonding strength between wafers and reduce the size and number of voids on the bonding interface. Additionally, with a selective etching operation depending the structural difference between the porous layer and the bulk layer, the uniformity of the film thickness is not adversely affected by fine particles that can be adhering to the porous Si layer.
However, a semiconductor substrate produced by a bonding process inevitably requires at least two wafers as starting materials, one of which is substantially wasted away in the course of polishing and etching to consume the limited natural resources almost for nothing. In other words, a SOI manufacturing process is required to realize low cost and economic feasibility in addition to an enhanced degree of process controllability and an improved uniformity of the film thickness.
Differently stated, the requirements of a process for manufacturing a high quality SOI substrate include an excellent reproducibility, an enhanced level of resource saving capability through the repeated use of a same wafer and low manufacturing cost.
Under these circumstances, the inventors of the present invention proposed in Japanese Patent Application Laid-Open No. 7-302889 a method of manufacturing a semiconductor substrate, with which a pair of substrates are bonded together and subsequently separated from each other through a porous layer arranged therebetween so that one of the substrates may be reused by removing the porous substance remaining on it. The disclosed method will now be summarily described below by referring to FIGS. 4A through 4C of the accompanying drawings.
It comprises steps of forming a porous layer 42 by transforming a surface layer of a first Si substrate 41 into a porous state, forming a single crystal Si layer 43 on the porous layer, bonding the single crystal Si layer to the main surface of a second Si substrate 44 with an insulation layer 45 interposed therebetween (FIG. 4A). It further comprises steps of separating the wafers bonded together with the porous layer arranged therebetween (FIG. 4B) and selectively removing the exposed porous Si layer on the surface of the second Si substrate to produce a SOI substrate (FIG. 4C). With this method, the first substrate 41 can be reused after removing the residual porous layer. The bonded wafers may be separated from each other typically by way of one of the following techniques;
The above listed techniques are based on the idea that, while the mechanical strength of the porous Si layer depends on the porosity of the layer, it is sufficiently lower than that of a bulk Si layer. As a rule of thumb, a porous Si layer having a porosity of 50% shows a mechanical strength about a half of that of a corresponding bulk Si layer. In short, when a pair of bonded wafers is subjected to compressive, tensile or shearing force, the porous Si layer will be destroyed to begin with. A porous layer showing a higher degree of porosity can be destroyed with less force.
However, in reality, efforts have been paid to reduce the porosity of the surface layer of the porous Si in order to realize an excellent epitaxial growth in terms of the quality of the device formed on the SOI substrate, while increasing the porosity of the inside of the porous Si for easy separation of the bonded wafers. Thus, as described in an example disclosed in Japanese Patent Application Laid-Open No. 7-302889, it has been a known practice to modify the porosity of the porous Si layer by controlling the electric current used in an anodization process.
On the other hand, Japanese Patent Application Laid-Open No. 8-213645 discloses a method of mechanically destroying a porous Si layer in order to separate a device forming layer from a substrate to which the former has been bonded, although it does not describe the configuration of the porous layer. Anyhow, conventionally, a pair of bonded substrates are separated along a porous layer arranged therebetween either by mechanically destroying the porous layer or by controlling the electric current used in an anodization process to modify the porosity of the porous layer.
Of these, the technique of applying external force to the bonded wafers to separate them along the porous layer disposed therebetween can result in unintended separation of the wafers along the bonded surfaces thereof if the bonding strength holding the wafers together is smaller than the mechanical strength of the porous Si layer or if the porous layer has one or more than one mechanically weak local regions. If a technique that does not involve a bonding process is employed, the process of separating the wafers along the porous layer has to be controlled rigorously in order to separate them mechanically without fail.
Japanese Patent Application Laid-Open No. 5-211128 proposes a method of separating a pair of bonded wafers comprising a step of forming a bubble layer by ion implantation and a subsequent step of crystal rearrangement and cohesion of bubbles by heat treatment so that the wafers may be peeled off from each other along the bubble layer. However, this method is accompanied by a problem of difficulty with which the heat treatment is optimized and the use of a low temperature range between 400 and 600.degree. C. It is not possible to suppress the above-described generation of voids with such a low temperature range, which voids cannot be eliminated if the bonded wafers are subjected to another heat treatment process after the formation of a thin film. In other words, the reduction in the size and number of voids is a phenomenon that appears when the pair of bonded wafers are heat treated at high temperature and would not occur if the bonded wafers are heat treated after the formation of a thin film. The net result of such an additional heat treatment will be an increased strength of the zone binding the wafers together. Additionally, this method involves a step of polishing the surfaces of the substrates after they are peeled off from each other, which step can degrade the distribution of film thickness.
As described above, each of the known techniques of separating a substrate along a porous layer is accompanied by its specific problems that have to be dissolved to adapt itself to the rapidly expanding applications of the bonded SOI technology, which will be summarily described below.
A light transmitting substrate typically made of glass plays an important role in a contact sensor comprising a light receiving device or a projection type liquid crystal image display apparatus. A high performance drive device is required to realize a higher density, an enhanced resolution and an improved definition for the pixels arranged in such a sensor or a display apparatus. To meet this requirement, it is necessary to form a single crystal layer on a light transmitting substrate so that the devices arranged on the substrate may also show an excellent crystallinity. Additionally, the use of such a single crystal layer makes it possible to implement a peripheral circuit for driving pixels and a circuit for processing images on a substrate carrying the pixels on it in order to downsize the chip and increase its operating speed.
However, a light transmitting substrate typically of glass can carry thereon only a non-crystalline thin Si layer or a polycrystalline thin Si layer at best to reflect the disorganized crystal structure of the substrate and hence such a substrate is not adapted to high performance devices. This is principally because the substrate shows a non-crystalline structure and hence cannot produce a high quality single crystal layer on it if a Si layer is formed thereon by deposition.
In other words, a non-crystalline Si layer or a polycrystalline Si layer is not adapted to produce a drive circuit on it that operates satisfactorily because of its defective crystal structure. This is why there is an ever-increasing demand for an advanced SOI technology for producing SOI substrates including bonded SOI substrates.
Although the use of a compound semiconductor substrate is indispensable for manufacturing a compound semiconductor device, compound semiconductor substrates are costly and mechanically not strong so that they are not adapted to producing large wafers. Therefore, efforts have been paid to produce a compound semiconductor by hetero-epitaxial growth on a Si wafer that can easily be made to have a large surface area.
While research is being made to epitaxially grow a compound semiconductor such as GaAs on a Si substrate, the grown film typically shows a poor crystallinity and hence is poorly adapted to being used for semiconductor devices mainly due to the difference in the lattice constant and the thermal expansion coefficient between them.
Meanwhile, research is also being made to epitaxially grow a compound semiconductor on a porous Si layer in order to mitigate the above identified lattice misfit. However, a porous Si layer is thermally unstable and can change with time so that it is not stable or reliable as a substrate during and after the operation of forming devices thereon. Thus, there is a need for a technology of producing a bonded SOI substrate with which a compound semiconductor is made to epitaxially grow on a porous Si layer and the grown compound semiconductor is transferred onto another substrate.